Method of forming self-aligned metal lines and vias

摘要

Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and patterned with one or more openings, each opening exposing one or more segments of the sacrificial material in one or more of the trenches, respectively. A sidewall spacer is formed in each opening and a selective etch process is performed to form one or more via holes that extend through the sacrificial material and through the lower portion of the dielectric layer below. Subsequently, all the sacrificial material is removed and metal is deposited, thereby forming self-aligned metal lines and via(s).

主权项

1. A method comprising:
forming a multi-layer stack comprising a first dielectric layer and a second dielectric layer above the first dielectric layer; forming a trench through the second dielectric layer and into an upper portion of the first dielectric layer; filling the trench with a sacrificial material; forming, on the stack, a mask with an opening aligned above a segment of the sacrificial material; forming a sidewall spacer in the opening such that a surface of the segment remains exposed; etching a via hole that extends through the segment and a lower portion of the first dielectric layer; and, removing all materials from above the second dielectric layer and any remaining sacrificial material.