Multi-bit non-volatile random-access memory cells

摘要

Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may also include multiple non-volatile storage elements. Each non-volatile storage element may be configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, allowing the multi-bit non-volatile random access memory cell to store/recall more than one databit per cell.

主权项

1. An apparatus, comprising:
a volatile storage element, the volatile storage element comprising a data true (DT) node and a data complement (DC) node; and a non-volatile storage circuit, the non-volatile storage circuit comprising at least one first pass transistor connected to the DT node of the volatile storage element and at least one second pass transistor connected to the DC node of the volatile storage element, the non-volatile storage circuit further comprising a plurality of non-volatile storage elements, each non-volatile storage element of the plurality of non-volatile storage elements configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, the non-volatile storage circuit further comprising a bridge transistor connected to two non-volatile storage elements, of the plurality of non-volatile storage elements, the bridge transistor configured to selectively connect one of the two non-volatile storage elements to the DT node of the volatile storage element via the at least one first pass transistor and the DC node of the volatile storage element via at least one second pass transistor.