Compression of integer data using a common divisor

摘要

According to one embodiment of the present invention, a system for compressing data determines a common divisor for a set of values comprising integers. The system divides each value within the set of values by the common divisor to produce reduced values, and represents the set of values in the form of data indicating the common divisor and the reduced values. Embodiments of the present invention further include a method and computer program product for compressing data in substantially the same manners described above.

主权项

1. A system for compressing a plurality of integer data values to produce reduced values and for decompressing the reduced values to reproduce the plurality of integer data values, the system comprising:
a compressor configured to:
receive the plurality of integer data values,determine a common divisor for the received plurality of data integer values,divide each integer data value within the plurality of integer data values by the common divisor to produce reduced values, andcompress the plurality of integer data values by representing the plurality of integer data values in a form of data indicating the common divisor and the reduced values, the common divisor being a product of powers of a predetermined set of numbers and data indicating the common divisor includes exponents for the predetermined set of numbers; and a hardware decompressor configured to receive a reduced value and the exponents for the predetermined set of numbers and to decompress the reduced value, the hardware decompressor comprising:
a plurality of hardware units, each of the plurality of hardware units being configured to receive a respective value and a respective exponent and produce an output representing a product of the respective value and a respective number of the predetermined set of numbers raised to a power indicated by the respective exponent, each of the plurality of hardware units including a plurality of times circuits implementing a left hardware shift, wherein:a first hardware unit is configured to receive the reduced value and a first exponent and produce an output representing a product of the reduced value and a first number of the predetermined set of numbers raised to a power indicated by the first exponent,a second hardware unit is configured to receive the output of the first hardware unit and a second exponent and produce an output representing a product of the output of the first unit and a second number of the predetermined set of numbers raised to a power indicated by the second exponent, anda third hardware unit is configured to receive the output of the second hardware unit and a third exponent and produce an output representing a product of the output of the second unit and a third number of the predetermined set of numbers raised to a power indicated by the third exponent.