| 摘要 |
Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution. |
| 主权项 |
1. A method comprising:
dividing, by a processor, a process distribution for an integrated circuit chip design into process windows; determining, by the processor, widths of distribution for a process parameter in the process windows, respectively, the process parameter impacting a timing parameter; based on the widths of distribution of the process parameter, assigning, by the processor, timing parameter adjustment factors to the process windows, respectively; performing, by the processor, a timing analysis of the integrated circuit chip design to acquire an initial solution for the timing parameter; for each specific process window, determining, by the processor, an adjusted solution for the timing parameter by adjusting the initial solution using a specific timing parameter adjustment factor assigned to the specific process window; and, given the adjusted solution for the timing parameter, predicting, by the processor, whether integrated circuit chips manufactured according to the integrated circuit chip design will meet a predetermined timing requirement. |
