FREQUENCY AND TIME DOMAIN STREAMING RECEIVER

摘要

A wideband signal processing receiver system including an interface for connecting to an analogue to digital converter (ADC) of a broader signal chain lineup, wherein the interface receives digital data from the ADC, and a field programmable gate array (FPGA) and associated configuration for converting the digital data into two digital signal paths. The two digital signal paths include a frequency domain path and an optionally decimated time domain path. A memory and/or high speed bus stores or transfers high speed bus/link data from the frequency domain path and the time domain path.

主权项

1. A wideband signal processing receiver system comprising:
an interface for connecting to an analogue to digital converter (ADC) of a broader signal chain lineup, wherein said interface receives digital data from said ADC; a field programmable gate array (FPGA) including a microprocessor and instructions executed by said microprocessor for converting said digital data into two digital signal paths, said two signal paths consisting of a frequency domain path and a time domain path; and a memory and/or high speed bus for storing data from said frequency domain path and said time domain path.