发明名称 LAYOUT STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION
摘要 A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.
申请公布号 US2017084604(A1) 申请公布日期 2017.03.23
申请号 US201514860788 申请日期 2015.09.22
申请人 UNITED MICROELECTRONICS CORP. 发明人 Tseng Pei-Shan;Liao Yu-Cheng;Chang Ping-Chen;Tang Tien-Hao;Su Kuan-Cheng
分类号 H01L27/02 主分类号 H01L27/02
代理机构 代理人
主权项 1. A layout structure, comprising: a substrate; a gate conductive layer formed on the substrate; a first doped region having a first conductivity and a second doped region having the first conductivity formed in the substrate and located at two sides of the gate conductive layer; a third doped region having a second conductivity formed in the substrate and adjacent to the second doped region, wherein the third doped region and the second doped region form a diode, the gate conductive layer, the first doped region and the third doped region are connected to ground, and the second doped region is connected to an input/output pad; a conductive layer formed on the substrate, wherein the conductive layer is located between the second doped region and the third doped region, and an additional conductive layer formed on the substrate, wherein the conductive layer and the additional conductive layer are both connected to ground.
地址 Hsinchu TW