EQUIVALENCE CHECKING OF ANALOG MODELS

摘要

Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.

主权项

1. A computer-implemented method for design analysis comprising:
extracting an input signal set using a first representation of a semiconductor circuit; creating a common input stimulus signal set for a second representation of the semiconductor circuit based on the input signal set extracted from the first representation of the semiconductor circuit; replaying the common input stimulus signal set against the second representation of the semiconductor circuit; generating first output waveforms for outputs of the first representation and second output waveforms for outputs of the second representation of the semiconductor circuit using the common input stimulus signal set; and performing equivalence checking between the first output waveforms and the second output waveforms.