发明名称 |
Methods and Systems for Correcting X-Pessimism in Gate-Level Simulation or Emulation |
摘要 |
Methods and systems are described to augment gate-level simulation with the ability to efficiently detect and correct X-pessimism on-the-fly. Using static Boolean analysis, gates are identified in the simulated hardware where there is potential for the simulator to propagate an X while the actual hardware propagates a 1 or 0, i.e. gates where X-pessimism potentially occurs. Data regarding potentially pessimistic gates is utilized in real time during simulation to determine actual pessimism at the gate and to correct it when it happens.;Whereas the understanding of X-pessimism and the method of augmenting simulation with attributes to correct X-pessimism in simulation on-the-fly is known in the public domain preceding known patents, various methods have been proposed recently to make on-the-fly X-pessimism correction more efficient for large ICs. The methods and systems described in the present invention, achieve new levels of performance and scalability of X-pessimism detection and correction. |
申请公布号 |
US2017083650(A1) |
申请公布日期 |
2017.03.23 |
申请号 |
US201615266455 |
申请日期 |
2016.09.15 |
申请人 |
Ashar Pranav |
发明人 |
Ashar Pranav;Guyler Ian Andrew;Mahajan Sanjeev |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. Computer and software systems with underlying methods for automatic X-pessimism correction during functional simulation or emulation of integrated circuit logic comprising automatic logical static analysis to determine potential X-pessimism nodes in combinational and sequential blocks. |
地址 |
Sunnyvale CA US |