发明名称 |
PREFETCHING ASSOCIATED WITH PREDICATED LOAD INSTRUCTIONS |
摘要 |
Technology related to prefetching data associated with predicated loads of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated load instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated load instruction and issue a prefetch request to a memory hierarchy of the processor for data at the calculated target address. |
申请公布号 |
WO2017048657(A1) |
申请公布日期 |
2017.03.23 |
申请号 |
WO2016US51418 |
申请日期 |
2016.09.13 |
申请人 |
MICROSOFT TECHNOLOGY LICENSING, LLC |
发明人 |
BURGER, Douglas C.;SMITH, Aaron L. |
分类号 |
G06F9/38;G06F9/30;G06F12/0862 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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