ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

摘要

An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.

主权项

1. An array substrate comprising:
a substrate; a first TFT formed on the substrate, the first TFT comprising a first channel layer formed on the substrate, a first gate insulator layer formed on the substrate and covering the first channel layer, a first gate electrode formed on the first gate insulator layer, a first dielectric layer formed on the first gate insulator layer and covering the first gate electrode, a second dielectric layer formed on the first dielectric layer; and a first source electrode and a first drain electrode formed on the second dielectric layer to electrically couple to the first channel layer; a second TFT formed on the substrate, the second TFT comprising a second gate insulator layer formed on the substrate, a second gate electrode formed on the second gate insulator layer, a third dielectric layer formed on the second gate insulator layer and covering the second gate electrode, a second channel layer formed on the third dielectric layer, and a second source electrode and a second drain electrode formed on the third dielectric layer to electrically couple to the second channel layer; and a third TFT formed on the substrate, the third TFT comprising a third gate insulator layer formed on the substrate, a third gate electrode formed on the third gate insulator layer, a fourth dielectric layer formed on the second gate insulator layer and covering the third gate electrode, a third channel layer formed on the fourth dielectric layer, and a third source electrode and a third drain electrode formed on the fourth dielectric layer to electrically couple to the third channel layer; wherein the first channel layer is made of a semiconducting material containing polycrystalline silicon; the second channel layer and the third channel layer are made of a semiconducting material containing metal oxide; the third dielectric layer is positioned between the second gate electrode and the second channel layer, and is in directly contact with the second gate electrode and the second channel layer; the fourth dielectric layer is positioned between the third gate electrode and the third channel layer, and is in directly contact with the third gate electrode and the third channel layer; the first dielectric layer is made of silicon nitride; the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are made of silicon oxide.