发明名称 |
DETECTING CIRCUIT DESIGN FLAWS BASED ON TIMING ANALYSIS |
摘要 |
An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data. |
申请公布号 |
US2017083658(A1) |
申请公布日期 |
2017.03.23 |
申请号 |
US201514858040 |
申请日期 |
2015.09.18 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Haller Wilhelm;Lind Kurt;Schroeder Friedrich;Zimmermann Stefan |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
1. A computer-implemented method of analyzing an end point report for a design of an electronic circuit, the computer-implemented method comprising:
loading, in a processing device, results of a static timing analysis run; selecting, by the processing device, a path from said loaded results; providing technology specific context data; determining, by the processing device, for one or more test points of the selected path, design quality parameters for determining a design problem area; and determining, for the design problem area, a root cause by analyzing design problem area data in comparison to related ones of said technology specific context data. |
地址 |
Armonk NY US |