REGISTER READ/WRITE ORDERING

摘要

Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.

主权项

1. An apparatus comprising a processor comprising one or more block-based processor cores, each of the cores being configurable to execute one or more instruction blocks, each of the cores comprising:
an execution unit configured to execute register read and write instructions contained in an instruction block to read from and/or write to, respectively, a register file comprising a plurality of registers; a hardware structure storing data indicative of an execution ordering of register read and write instructions; and a control unit configured to control issuing of register read and write instructions to the execution unit based at least in a part on the hardware structure data.