发明名称 METHOD OF MAKING SELF-ASSEMBLING FLOATING GATE ELECTRODES FOR A THREE-DIEMNSIONAL MEMORY DEVICE
摘要 Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer material layers between insulating layers, depositing a continuous metal layer, and inducing diffusion and agglomeration of the metal into the lateral recesses to form discrete metal portions employing an anneal process. The metallic material can migrate and form the discrete metal portions due to surface tension, which operates to minimize the surface area of the metallic material. Optionally, two or more continuous metal layers can be employed to form discrete metal portions including at least two metals. Optionally, a selective metal deposition process can be performed to deposit additional metal portions including a different metallic material on the discrete metal portions. The metal floating gate electrodes can be formed without employing an etch process. A tunneling dielectric layer and a semiconductor channel can be subsequently formed.
申请公布号 US2017084623(A1) 申请公布日期 2017.03.23
申请号 US201615056465 申请日期 2016.02.29
申请人 SANDISK TECHNOLOGIES INC. 发明人 SHARANGPANI Rahul;PERI Somesh;MAKALA Raghuveer S.;ZHANG Yanli
分类号 H01L27/115;H01L21/28;H01L29/423 主分类号 H01L27/115
代理机构 代理人
主权项 1. A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack and comprising lateral protrusions at levels of the electrically conductive layers; a blocking dielectric layer contacting a sidewall of the memory opening; metal floating gate structures located inside the blocking dielectric layer within volumes of the lateral protrusions of the memory opening and including a respective convex inner sidewall; a tunneling dielectric layer contacting vertical inner sidewall portions of the blocking dielectric layer and located inside the metal floating gate structures; and a vertical semiconductor channel contacting an inner sidewall of the tunneling dielectric layer.
地址 PLANO TX US