INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR

摘要

In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.

主权项

1. An apparatus for use with a memory having memory cells arranged in rows and columns of memory cells and including spare memory cells, comprising:
an internal self-test logic circuit built in within the apparatus, the self-test logic circuit including: a test pattern generator for generating test patterns and for testing memory cells within the memory using the generated test patterns; wherein the test pattern generator includes a plurality of generators including at least one address generator configured to generate a pattern of memory cell addresses in response to an address instruction to traverse a memory region of a plurality of memory cells wherein each memory cell address includes a row address of row address bits and a column address of column address bits, and at least one data generator configured to generate in response to a data instruction, a pattern of data for a pattern of test data, to be written in memory cells addressed by a pattern of memory cell addresses generated by the address generator wherein the generated pattern of data is a selectable function of the pattern of memory cell addresses of the memory cells in which the generated pattern of data is to be written.