INTEGRATED CIRCUIT WITH LOW LATENCY AND HIGH DENSITY ROUTING BETWEEN A MEMORY CONTROLLER DIGITAL CORE AND I/OS

摘要

An integrated circuit is provided with a memory controller coupled to a buffered command and address bus and a pipelined data bus having a pipeline delay. The memory controller is configured to control the write and read operations for an external memory having a write latency period requirement. The memory controller is further configured to launch write data into the pipelined data bus responsive to the expiration of a modified write latency period that is shorter than the write latency period.

主权项

1. An integrated circuit, comprising:
a buffered command and address (CA) bus; a pipelined data (DQ) write bus having a pipeline delay; and a memory controller configured to drive a write command signal into the buffered CA bus at an initial time, wherein the memory controller is further configured to determine a delay difference period between a write latency requirement for an external memory and the pipeline delay and to drive a DQ signal into the pipelined DQ write bus at an expiration of the delay difference period.