MULTIMODAL TARGETS IN A BLOCK-BASED PROCESSOR

摘要

Apparatus and methods are disclosed for decoding targets from an instruction and transmitting data to those targets in accordance with a current instruction. Multimodal target hardware is used in conjunction with one or more of the routers so as to route data to an appropriate target. The data can be one or more operands or a predicate and the targets can include operand buffers, broadcast channels, and general registers. In this way, operands, for example, can be directed for use with multiple subsequent instructions, and there are multiple modes for distributing the operands to the multiple instructions.

主权项

1. An apparatus comprising one or more block-based processor cores, at least one of the processor cores comprising:
one or more routers configured to route data associated with instructions within an instruction block to one or more other instructions; a control unit coupled to the one or more routers and configured to cause the processor core to execute a current instruction within the instruction block and to decode a target field from the current instruction, the control unit further configured to control the one or more routers to route data associated with the current instruction to any of three or more different target types in accordance with the target field.