| 摘要 |
When two or more pipelines are arranged in a processor and the processor encounters a branch instruction in an instruction fetching stage, two or more pipelines are simultaneously loaded to enter different parallel pipelines; and; when a computation result of the branch instruction is obtained, execution is continued if the computation result of the branch instruction is to select a currently executed pipeline; and switching to a selected pipeline is performed to continue the execution if the computation result is to select one pipeline among the rest of the pipelines. When the processor performs branch prefetching, because there is no complicated algorithm, time overheads and wrong prediction of the branch prediction mode, the processor can operate in a high speed. |
