发明名称 増幅回路および窒化物半導体装置
摘要 PROBLEM TO BE SOLVED: To suppress reduction in output power or reduction in gain at a large power input, and to suppress reduction in gain or deterioration in distortion characteristics in the case that drift of a drain idle current is generated.SOLUTION: An amplifier circuit comprises: a power amplifier 11 including an FET 10 having an Si substrate or an SiC substrate and a nitride semiconductor layer formed on the Si substrate or the SiC substrate and having a gate terminal to which a high-frequency signal is input; a detector 12 detecting a drain idle current of the power amplifier; and a controller 14 outputting a gate bias voltage depending on the drain idle current to the gate terminal of the power amplifier in the case that the detected drain idle current is smaller than a predetermined value, and outputting a fixed gate bias voltage to the gate terminal of the power amplifier in the case that the detected drain idle current is the predetermined value or more.
申请公布号 JP6097961(B2) 申请公布日期 2017.03.22
申请号 JP20110141102 申请日期 2011.06.24
申请人 住友電工デバイス・イノベーション株式会社 发明人 宮澤 直行
分类号 H03F1/32;H03F1/02;H03F3/24 主分类号 H03F1/32
代理机构 代理人
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