发明名称 半導体装置及び半導体装置の製造方法
摘要 Disclosed is a semiconductor device in which, when two adjacent semiconductor chips are coupled with bonding wires, a short circuit between the adjacent bonding wires can be suppressed. A first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along a first side. When viewed from a direction perpendicular to a chip mounting part, a maximum of the space between the first bonding wire and the second bonding wire is larger than that of the space between the second bonding wire and the third bonding wire. Further, a maximum of the space between the second bonding wire and the third bonding wire is larger than that of the space between the third bonding wire and the fourth bonding wire.
申请公布号 JP6100648(B2) 申请公布日期 2017.03.22
申请号 JP20130176723 申请日期 2013.08.28
申请人 ルネサスエレクトロニクス株式会社 发明人 浅村 規弘;石野 能広
分类号 H01L25/04;H01L21/60;H01L23/28;H01L25/18 主分类号 H01L25/04
代理机构 代理人
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