发明名称 |
Method for fabricating semiconductor device |
摘要 |
A method for fabricating a semiconductor device includes: forming isolation layers and active regions in a substrate, wherein each of the active regions is formed between the isolation layers; forming a silicide layer in each of the active regions; forming trenches and silicide layer patterns simultaneously by etching the silicide layer and each of the active regions, wherein each of the trenches is located between the silicide layer patterns; forming a buried gate in each of the trenches; forming an inter-layer dielectric layer that covers the buried gate and the silicide layer patterns; and forming a first opening that exposes one silicide layer pattern among the silicide layer patterns by selectively etching the inter-layer dielectric layer, wherein the silicide layer patterns are formed before the buried gate is formed. |
申请公布号 |
US9601588(B2) |
申请公布日期 |
2017.03.21 |
申请号 |
US201414572498 |
申请日期 |
2014.12.16 |
申请人 |
SK Hynix Inc. |
发明人 |
Kim Hyung-Kyun |
分类号 |
H01L29/423;H01L29/78;H01L21/762;H01L27/108;H01L29/66 |
主分类号 |
H01L29/423 |
代理机构 |
IP & T Group LLP |
代理人 |
IP & T Group LLP |
主权项 |
1. A method for fabricating a semiconductor device, comprising:
forming isolation layers and active regions in a substrate, wherein each of the active regions is formed between the isolation layers; forming a silicide layer in each of the active regions; forming trenches and silicide layer patterns simultaneously by etching the silicide layer in each of the active regions, wherein each of the trenches is located between the silicide layer patterns; forming a buried gate in each of the trenches; forming an inter-layer dielectric layer that covers the buried gate and the silicide layer patterns; and forming a first opening that exposes one silicide layer pattern among the silicide layer patterns by selectively etching the inter-layer dielectric layer, wherein the silicide layer patterns are formed before the buried gate is formed. |
地址 |
Gyeonggi-do KR |