Frequency synthesis for memory input-output operations

摘要

A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

主权项

1. An apparatus comprising:
a memory array; an input/output (I/O) lane coupled to the memory array, wherein the I/O lane is configured to provide data signals to and from the memory array; and a first clock circuit coupled to the I/O lane, wherein the first clock circuit is configured to provide a first internal clock signal to the I/O lane, wherein the first clock circuit is further configured to synthesize the first internal clock signal based, at least in part, on the data signals provided to the I/O lane.