发明名称 |
Diode structure compatible with FinFET process |
摘要 |
An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process. |
申请公布号 |
US9601627(B2) |
申请公布日期 |
2017.03.21 |
申请号 |
US201615181232 |
申请日期 |
2016.06.13 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Tsai Tsung-Che;Chang Yi-Feng;Lee Jam-Wem |
分类号 |
H01L29/76;H01L29/78;H01L29/739;H01L29/66;H01L29/423 |
主分类号 |
H01L29/76 |
代理机构 |
Slater Matsil, LLP |
代理人 |
Slater Matsil, LLP |
主权项 |
1. An integrated circuit comprising:
a fin; a first source/drain region in the fin, the first source/drain region having a first conductivity type; a second source/drain region in the fin, the second source/drain region having a second conductivity type, the first conductivity type being different than the second conductivity type; a channel region interposed between the first source/drain region and the second source/drain region, the channel region having the second conductivity type, the second source/drain region having a higher dopant concentration of the second conductivity type than the channel region; and a gate over the channel region, the gate having a first edge closest to the first source/drain region and a second edge closest to the second source/drain region, wherein the first edge is laterally offset from an interface between the channel region and the first source/drain region in a plan view, wherein the gate and the second source/drain region are electrically coupled. |
地址 |
Hsin-Chu TW |