发明名称 Hazard check instructions for enhanced predicate vector operations
摘要 A hazard check instruction has operands that specify addresses of vector elements to be read by first and second vector memory operations. The hazard check instruction outputs a dependency vector identifying, for each element position of the first vector corresponding to the first vector memory operation, which element position of the second vector that the element of the first vector depends on (if any). In an embodiment, at least one of the vector memory operations has addresses specified using a scalar address in the operands (and a vector attribute associated with the vector). In an embodiment, the operands may include predicates for one or both of the vector memory operations, indicating which vector elements are active. The dependency vector may be qualified by the predicates, indicating dependencies only for active elements.
申请公布号 US9600280(B2) 申请公布日期 2017.03.21
申请号 US201314034651 申请日期 2013.09.24
申请人 Apple Inc. 发明人 Gonion Jeffry E.
分类号 G06F9/30;G06F15/80;G06F9/38 主分类号 G06F9/30
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. ;Merkel Lawrence J.
主权项 1. A processor comprising: an execution core configured to execute an instruction having a plurality of operands stored in a plurality of operand registers identified by the instruction, wherein: the plurality of operands of the instruction specify a first one or more addresses and a second one or more addresses;at least the first one or more addresses are contiguous in an address range;the address range begins at a scalar address that is included in the plurality of operands of the instruction;the address range ends at a second address determined from the scalar address and a vector attribute that is stored in one of the plurality of operand registers identified by the instruction, wherein the vector attribute specifies size information of a first vector having vector elements stored in the address range; andthe execution core is configured, responsive to executing the instruction, to:detect whether or not a dependency exists between the first one or more addresses specified by the plurality of operand of the instructions and the second one or more addresses specified by the plurality of operands of the instruction; andgenerate a dependency vector that indicates, for each first element of the first vector stored in the address range that depends on a second element of a second vector having elements stored at the second one or more addresses, which second element that the first element depends on.
地址 Cupertino CA US