One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same

摘要

A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

主权项

1. A one time programmable (OTP) memory cell, comprising:
a substrate structure; a shallow trench insulation area adjoining the substrate structure; a select gate transistor formed on the substrate structure, the select gate transistor having a first gate terminal, a first drain terminal, and a first source terminal; a following gate transistor formed on the substrate structure, the following gate transistor having a second gate terminal, a second drain terminal, and a second source terminal coupled to the first drain terminal; an antifuse varactor formed on the substrate structure, the antifuse varactor having a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal; and a dummy transistor partially formed on the substrate structure, the dummy transistor having a fourth gate terminal, and a fourth source terminal coupled to the third drain terminal; wherein a part of the fourth gate terminal is formed above the shallow trench insulation area.