发明名称 Semiconductor package
摘要 A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.
申请公布号 US9601450(B2) 申请公布日期 2017.03.21
申请号 US201514669491 申请日期 2015.03.26
申请人 J-DEVICES CORPORATION 发明人 Miyakoshi Takeshi;Hosoyamada Sumikazu;Kumagaya Yoshikazu;Chikai Tomoshige;Nakamura Shingo;Matsubara Hiroaki;Sakumoto Shotaro
分类号 H01L23/48;H01L23/52;H01L23/00;H01L23/36;H01L23/367;H01L23/498;H01L21/48;H01L25/10 主分类号 H01L23/48
代理机构 Maier & Maier, PLLC 代理人 Maier & Maier, PLLC
主权项 1. A stacked semiconductor package, comprising: a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; wherein: the first semiconductor package further includes: a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin and located above the first semiconductor element and located in a region above a region between two ends of the first semiconductor element; and a thermal via connected to the conductive layer and located on the first circuit board in an area where the first semiconductor is not located, the conductive layer and thermal via configured to allow heat generated from the first semiconductor element to escape below the first semiconductor package.
地址 Oita JP