发明名称 Semiconductor manufacturing for forming bond pads and seal rings
摘要 An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.
申请公布号 US9601354(B2) 申请公布日期 2017.03.21
申请号 US201414470383 申请日期 2014.08.27
申请人 NXP USA, Inc. 发明人 Reber Douglas M.;Ajuria Sergio A.;Nguyen Phuc M.
分类号 H01L21/66;H01L21/48;H01L23/00;H01L23/522;H01L23/58 主分类号 H01L21/66
代理机构 代理人
主权项 1. A method for making integrated circuits using a semiconductor substrate, the method comprising: etching a first pad opening to a first depth into a plurality of build-up layers including interlayer dielectric layers and metal layers that are over the semiconductor substrate; depositing a conductive layer over the plurality of build-up layers, including over the first pad opening and along sidewalls of the first pad opening; and etching the conductive layer to leave a remaining portion of the conductive layer over the first pad opening, along the sidewalls of the first pad opening, and extending over a portion of a top surface of the plurality of build-up layers to form a first bond pad within the first pad opening; wherein the first depth is located at a transition layer of the plurality of build-up layers and the transition layer comprises an isolation dielectric layer, an interconnect structure is exposed in a first sidewall of the first pad opening, and the conductive layer is conformal deposited over the first pad opening, including over the isolation dielectric layer within the first pad opening and along the sidewalls of the first pad opening, to form a connection with the interconnect structure.
地址 Austin TX US