Repeater insertions providing reduced routing perturbation caused by flip-flop insertions

摘要

System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to accommodate potential flip-flop insertions. The sufficient spacing between the repeaters in combination with the staggered pattern ensures that flip-flop insertions can be performed at any of the repeater locations without space limitation. When rerouting is needed following a flip-flop insertion on an interconnect, automatic rerouting is performed but restricted to a short and specified region along the interconnect. Thereby, the resulted alteration from the current routing configuration is minimal and deterministic.

主权项

1. A method of placing repeaters in interconnects in physical design of an integrated circuit, said method comprising:
accessing a first routing configuration of said interconnects of said integrated circuit; determining locations in said interconnects for inserting a plurality of repeaters according to timing requirements; and inserting said plurality of repeaters at determined locations, wherein repeaters in adjacent interconnects are disposed in a staggered pattern, and wherein further disposing said plurality of repeaters in said staggered pattern comprises disposing two adjacent repeaters of said repeaters in said adjacent interconnects at an offset from each other, said offset being at least a size of a standard flip-flop.