High performance interconnect physical layer

摘要

A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.

主权项

1. An apparatus comprising:
a layered stack comprising physical layer logic, link layer logic, and protocol layer logic, wherein the physical layer logic is to generate a supersequence comprising a repeating sequence comprising an electrical ordered set (EOS) followed by a plurality of training sequences, the plurality of training sequences comprises a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header, the training sequence header is to identify a type of the corresponding training sequence, and the training sequence header is to be DC-balanced over the plurality of training sequences.