| 摘要 |
An analog circuit for generating a periodic signal at a selected phase, including one or more phase interpolators that receive orthogonal differential RF signals and a pair of differential gain signals. The differential in-phase RF signal is applied at respective gates of tail transistors, and a first differential gain signal is applied across gates of a transistor pair coupled to each of the tail transistors. The quadrature-phase RF signal and a second differential gain signal is similarly applied to another quad of transistors (i.e., pair of transistor pairs) and associated tail transistors. A load connected to the one transistor in each pair receives the output signal, at a phase corresponding to a ratio of the first and second gain signals. The gain signals may be DC or AC, which allows configuration of the circuit as a phase shifter or an upconversion mixer, and the load may be presented by a transform in which the phase also depends on the relative coupling from the in-phase and quadrature-phase sides of the phase interpolator. |
| 主权项 |
1. An analog circuit for generating a periodic signal, comprising:
oscillator circuitry for generating first and second periodic differential signals at a first frequency and at a selected phase angle relative to one another; at least one phase interpolator, having inputs receiving the first and second periodic differential signals, and having inputs receiving first and second differential gain signals, for generating a combined periodic signal having a frequency component corresponding to the first frequency and at a phase angle corresponding to a relationship of the first and second differential gain signals, wherein the at least one phase interpolator comprises:
a load;a plurality of transistor pairs, each comprising first and second transistors, each having a conduction path and a gate, a first end of the conduction path of each of the first and second transistors connected at a common node, a second end of the conduction path of the first transistor coupled to the load, and a second end of the conduction path of the second transistor coupled to a bias voltage; anda plurality of tail transistors, each associated with one of the transistor pairs, and each having a conduction path and a gate, a first end of the conduction path coupled to the common node of an associated one of the plurality of transistor pairs, a second end of the conduction path coupled to a reference voltage; wherein the first differential gain signal is applied across the gates of the first and second transistors in first and second ones of the transistor pairs; wherein the second differential gain signal is applied across the gates of the first and second transistors in each of third and fourth ones of the transistor pairs; wherein the first periodic differential signal is applied across the gates of a first tail transistor associated with the first transistor pair, and of a second tail transistor associated with the second transistor pair; and wherein the second periodic differential signal is applied across the gates of a third tail transistor associated with the third transistor pair, and of a fourth tail transistor associated with the fourth transistor pair. |
