发明名称 Testing device for validating stacked semiconductor devices
摘要 Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.
申请公布号 US9599661(B2) 申请公布日期 2017.03.21
申请号 US201213629273 申请日期 2012.09.27
申请人 Intel Corporation 发明人 Wig Timothy D.
分类号 G01R31/00;G01R31/28 主分类号 G01R31/00
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. An apparatus, comprising: a device port to receive a semiconductor device; a test instrument interface to receive a test instrument interconnect; and, a testing board interconnecting the device port and the test instrument socket, the testing board formed from a High Density Interconnect (HDI) substrate, the High Density Interconnect substrate comprising multiple signal plane layers, the High Density Interconnect substrate comprising at least one signal wiring path connecting said device port and said test instrument socket having a micro-via that extends on one end from a signal wire along one of said plane layers through first and second ones of said signal plane layers to said device port, wherein said micro via does not extend completely through said HDI substrate, said device port located on an upper level of said testing board, said micro via residing beneath a region of said upper level where the semiconductor device is to be placed over the testing board by way of its connection to the device port, said micro-via not extending to said upper level.
地址 Santa Clara CA US