Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabrication

摘要

Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in which economical and environmentally friendly chemical mechanical polishing techniques are implemented to minimize waste of, e.g., III-V precursor material, minimize production costs, and minimize environmental impact from toxic waste generated from chemical mechanical polishing of III-V films.

主权项

1. A method, comprising:
forming an insulating layer on a semiconductor substrate, wherein the insulating layer comprises a trench and an open region formed in the insulating layer down to the semiconductor substrate; performing an epitaxial deposition process to deposit compound semiconductor material in the trench and in the open region of the insulating layer; terminating the epitaxial deposition process at some point in the deposition process when the trench is over filled with the compound semiconductor material, thereby forming excess compound semiconductor material protruding from the trench, and the open region is partially filled with the compound semiconductor material; depositing a layer of sacrificial material on the surface of the insulating layer to cover the excess compound semiconductor material protruding from the trench and to fill a remaining portion of the open region with the sacrificial material; and performing a CMP (chemical mechanical polishing) process to form a planarized surface by removing the sacrificial material on the surface of the insulating layer and removing the excess compound semiconductor material protruding from the trench.