Error detection and correction circuitry

摘要

Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

主权项

1. An integrated circuit comprising:
a memory array having a first set of memory elements arranged along a first column and a second set of memory elements arranged along a second column; a multiplexing circuit coupled between the first set of memory elements and the second set of memory elements; a first circuit operable to detect errors in the first and second sets of memory elements; a second circuit operable to locate and correct the detected errors in the first and second sets of memory elements; and control circuitry coupled to the first and second circuits, wherein the control circuitry is operable to control the second circuit to locate and correct the detected errors in response to detecting errors using the first circuit.