发明名称 |
Decoding circuit and method of decoding signal |
摘要 |
A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information. |
申请公布号 |
US9602094(B2) |
申请公布日期 |
2017.03.21 |
申请号 |
US201514713854 |
申请日期 |
2015.05.15 |
申请人 |
SK Hynix Inc. |
发明人 |
Jang Dong-Wook |
分类号 |
H03D3/00;H03K9/08;H03D3/04;H03D3/20;H03L7/099 |
主分类号 |
H03D3/00 |
代理机构 |
IP & T Group LLP |
代理人 |
IP & T Group LLP |
主权项 |
1. A decoding circuit comprising:
a section information generation unit suitable for generating section information corresponding to a length of a section in which an input signal has a first value; a period information generation unit suitable for generating period information corresponding to a length of a period of the input signal; a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value; and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information, wherein the section information generation unit comprises: a first period signal generation unit suitable for generating a first period signal toggling with a preset period during the section in which the input signal has the first value; and a first counter suitable for generating the section information by performing a counting operation in response to the first period signal. |
地址 |
Gyeonggi-do KR |