| 发明名称 | Systems and methods for reordering packet transmissions in a scalable memory system protocol | ||
| 摘要 | A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The processor may receive a plurality of packets associated with a plurality of data operations, such that each of the plurality of packets includes a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet. The processor may also perform the plurality of data operations in a first order based on the type of memory component indicated in the transaction window field of each of the plurality of packets. | ||
| 申请公布号 | US9600191(B2) | 申请公布日期 | 2017.03.21 |
| 申请号 | US201514724489 | 申请日期 | 2015.05.28 |
| 申请人 | Micron Technology, Inc. | 发明人 | Pawlowski J. Thomas |
| 分类号 | G06F3/06;H04L12/801;H04L12/825;H04L12/873;G06F11/10;G06F11/07;G11C29/52;H04L1/18 | 主分类号 | G06F3/06 |
| 代理机构 | Fletcher Yoder, P.C. | 代理人 | Fletcher Yoder, P.C. |
| 主权项 | 1. A memory device comprising: a plurality of memory components configured to store data; a processor communicatively coupled to the plurality of memory components, wherein the processor is configured to: receive a plurality of packets associated with a plurality of data operations, wherein each of the plurality of packets comprises a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet; and perform the plurality of data operations in an order based on the type of memory component indicated in the transaction window field of each of the plurality of packets. | ||
| 地址 | Boise ID US | ||