NAND array comprising parallel transistor and two-terminal switching device

摘要

Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.

主权项

1. A memory device, comprising:
an array of memory cells comprising:
an array of transistor components; andan array of two-terminal multi-state components, wherein:
the array of memory cells is arranged electrically in series from respective first terminals to respective second terminals of respective ones of the memory cells,a transistor component of the array of transistor components is connected electrically in parallel with a two-terminal multi-state component of the array of two-terminal multi-state components and wherein the transistor component is formed at least in part within a substrate of the memory;a signal applied to the array of memory cells propagates through the at least one of the memory cells primarily via the transistor component in response to the transistor component being activated, andthe signal propagates through the at least one of the memory cells primarily via the two-terminal multi-state component in response to the transistor component being de-activated; and a second array of memory cells, further wherein:
the array of memory cells and the second array of memory cells terminate at respective select transistors that are connected to a first bitline and to a second bitline, respectively, and further wherein the respective select transistors are commonly activated by a word line,the two-terminal multi-state component of the array of two-terminal multi-state components is configured to be programmed or erased in response to activation of the wordline and in response to application of the signal at the first bitline, andapplication of an inhibit signal to the second bitline mitigates programming or erasing of the second array of memory cells in response to activation of the wordline.