Memory bank signal coupling buffer and method

摘要

A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

主权项

1. An apparatus comprising:
a plurality of data lines configured to provide respective signals within a plurality of memory cells, a data line of the plurality of data lines being divided into a plurality of data line segments; and a bidirectional buffer interposed in the data line and connecting two data line segments of the plurality of data line segments to each other, the bidirectional buffer configured to bi-directionally provide data between the two data line segments, wherein the bidirectional buffer is configured, responsive to receiving a first data signal indicative of a precharge mode, to decouple the two data line segments from each other by disabling a first transistor coupled to a first of the two data line segments and disabling a second transistor coupled to a second of the two data line segments, wherein the bidirectional buffer is configured, responsive to receiving a second data signal indicative of an operation mode, to couple the first of the two data line segments to the second of the two data line segments by enabling the first transistor and enabling a third transistor via the enabled first transistor, and wherein the third transistor is coupled to the second data line segment.