Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof

摘要

An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.

主权项

1. An integrated circuit comprising:
a scan chain having a first plurality of dual edge flip flops and a second plurality of dual edge flip flops, wherein each dual edge flip flop of the first and second pluralities of dual edge flip flops includes a data input, a scan input, a clock input, and data output, the scan chain to receive a test pattern at the scan input that is synchronous with a test clock during a shift phase of scan testing; a clock divider circuit coupled to receive the test clock and configured to divide the test clock to provide a divided test clock having a lower frequency than the test clock; clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock input of the scan chain based on the scan enable signal, wherein the divided test clock is provided to the clock input of the scan chain during the shift phase of scan testing; and second clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to receive a second system dock, a control input coupled to receive the scan enable signal, and an output configured to provide the divided test clock as a second clock signal to the clock input of each dual edge flip flop of the second plurality of dual edge flip flops when the scan enable signal has the first value, and to provide the second system clock as the clock signal to the clock input of each dual edge flip flop of the second plurality of dual edge flip flops when the scan enable signal has the second value wherein the second system clock is 90 degrees out of phase with the system clock.