发明名称 Result bypass cache
摘要 A system and method for efficiently accessing operands in a datapath. An apparatus includes a data operand register file and an execution pipeline with multiple stages. In addition, the apparatus includes a result bypass cache configured to store data results conveyed by at least the final stage of the execution pipeline stage. Control logic is included which is configured to determine whether source operands for an instruction entering the pipeline are available in the last stage of the pipeline or in the result bypass cache. If the source operands are available in the last stage of the pipeline or the result bypass cache, they may be obtained from one of those locations rather than reading from the register file. If the source operands are not available from the last stage or the result bypass cache, then they may be obtained from the data operand register file.
申请公布号 US9600288(B1) 申请公布日期 2017.03.21
申请号 US201213465372 申请日期 2012.05.07
申请人 Apple Inc. 发明人 Potter Terence M.;Olson Timothy A.;Blomgren James S.;Drebin Robert A.;Youngwith Douglas C.;Loschke Jon A.
分类号 G06F9/38 主分类号 G06F9/38
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Rankin Rory D.;Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
主权项 1. An apparatus comprising: a data operand register file; one or more execution pipeline stages; an operand cache configured to store data results conveyed by the one or more execution pipeline stages; and control logic, wherein the control logic is configured to: select a source for a data operand of an instruction from the operand cache or a given stage of the pipeline, in response to determining the data operand is available in the operand cache or the given stage of the pipeline;select a source for a data operand of an instruction from the data operand register file, in response to determining the data operand is not available in either the operand cache or the given stage of the pipeline;write a result of a producer instruction into the operand cache from the one or more execution pipeline stages when a distance between the producer instruction and a consumer instruction is less than a given distance, wherein the distance is measured as a number of instructions in-program-order between the producer instruction and the consumer instruction; andprevent writing the result into the operand cache and write the result into the data operand register file when the distance is greater than the given distance.
地址 Cupertino CA US