发明名称 Semiconductor memory system including a plurality of semiconductor memory devices
摘要 A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
申请公布号 US9601206(B2) 申请公布日期 2017.03.21
申请号 US201414539522 申请日期 2014.11.12
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Shibata Noboru;Sukegawa Hiroshi
分类号 G11C7/00;G11C16/10;G11C11/56;G11C16/04;G11C16/30 主分类号 G11C7/00
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A semiconductor memory system comprising: a first semiconductor memory device; a second semiconductor memory device; and a controller electrically connected to the first and second semiconductor memory devices, wherein when one of the first and second semiconductor memory devices consumes a current larger than a reference current, the controller controls the other of the first and second semiconductor memory devices to a waiting state.
地址 Minato-ku JP