发明名称 Semiconductor device and method for fabricating the same
摘要 The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
申请公布号 US9601632(B2) 申请公布日期 2017.03.21
申请号 US201314021618 申请日期 2013.09.09
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Yamazaki Shunpei;Suzawa Hideomi;Sasagawa Shinya;Kurata Motomu;Tsubuku Masashi
分类号 H01L29/786;H01L29/66 主分类号 H01L29/786
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device, comprising: a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer, wherein the source electrode layer comprises a first region and a second region, wherein the drain electrode layer comprises a third region and a fourth region, wherein the second oxide layer is in direct contact with a top surface of the first region and a top surface of the third region, wherein each of the first region and the third region are in direct contact with a top surface of the oxide semiconductor layer, wherein the second region and the fourth region do not overlap with the second oxide layer and the gate insulating layer, and wherein a side surface of the second oxide layer and a side surface of the gate insulating layer are aligned over the source electrode layer and the drain electrode layer.
地址 Atsugi-shi, Kanagawa-ken JP