| 发明名称 |
MANAGING POWER-DOWN MODES |
| 摘要 |
An apparatus includes a first circuit configured to receive one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The first circuit further selects one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes. A second circuit is configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores. |
| 申请公布号 |
US2017075408(A1) |
申请公布日期 |
2017.03.16 |
| 申请号 |
US201615010237 |
申请日期 |
2016.01.29 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
BANERJEE Sarbartha;MISRA Rakesh |
| 分类号 |
G06F1/32 |
主分类号 |
G06F1/32 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a first circuit configured to
receive one or more requests from a plurality of cores, each of the one or more requests being to enter or to exit one of a plurality of power-down modes, andselect one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes; and a second circuit configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores. |
| 地址 |
San Diego CA US |
