CHARGE STORAGE FERROELECTRIC MEMORY HYBRID AND ERASE SCHEME

摘要

A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.

主权项

1. A method of inhibiting programming of a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs, each FeFET comprising a gate stack, a source, a drain, a channel and a bulk substrate region, wherein the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel, the method comprising:
inhibiting programming of those FeFET memory cells not selected for programming and adjacent to those FeFET memory cells selected for programming by applying a voltage less in absolute magnitude than the program voltage to the gate, source and drain regions of the adjacent FeFET memory cells, wherein the program voltage is positive or negative depending on the channel doping type; and holding the bulk substrate regions at a ground state during said applying of the program voltage to the gate, source and drain regions of the adjacent FeFET memory cells.