发明名称 SIGNAL PROCESSING CIRCUIT
摘要 Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.
申请公布号 US2017075687(A1) 申请公布日期 2017.03.16
申请号 US201615360028 申请日期 2016.11.23
申请人 Renesas Electronics Corporation 发明人 YAMASAKI Hiroyuki;NODA Hideyuki;MURATA Kan
分类号 G06F9/30;G06F13/40;G06F13/36;G05B19/042 主分类号 G06F9/30
代理机构 代理人
主权项 1. A microcontroller comprising: a signal processing unit; a central processing unit (CPU) that sends a plurality of commands to the signal processing unit; and a bus coupled to the CPU and the signal processing unit, wherein the signal processing unit includes a first sequencer, a second sequencer, an arbitration circuit and a common arithmetic unit, wherein the first sequencer requests the common arithmetic unit to execute a first request among the plurality of commands, wherein the second sequencer requests the common arithmetic unit to execute a second request among the plurality of commands, and wherein the arbitration circuit selects one of the first request and the second request when the first and second requests compete against each other.
地址 Tokyo JP