发明名称 |
STRUCTURE AND METHOD OF OPERATION FOR IMPROVED GATE CAPACITY FOR 3D NOR FLASH MEMORY |
摘要 |
Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure. |
申请公布号 |
US2017077118(A1) |
申请公布日期 |
2017.03.16 |
申请号 |
US201514854383 |
申请日期 |
2015.09.15 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
CHENG CHENG-HSIEN;LEE CHIH-WEI;KU SHAW-HUNG;LU WEN-PIN |
分类号 |
H01L27/115 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
1. A three-dimensional memory cell comprising:
a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer, wherein the first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure. |
地址 |
Hsin-Chu TW |