This solid-state imaging element is provided with a P-type substrate (11) and a wiring layer (17). The substrate (11) is provided with: an N-type semiconductor region (12) that is arranged in a first main surface (S1) and extends in the direction from the first main surface (S1) toward a second main surface (S2); an N-type semiconductor region (13) that is arranged between the second main surface (S2) and the N-type semiconductor region (12) and is connected to the N-type semiconductor region (12); a P-type semiconductor region (14) that is arranged between the second main surface (S2) and the N-type semiconductor regions (13) of a pixel (1) and a pixel (2); an N-type well (15) that is arranged in the first main surface (S1) between the N-type semiconductor region (12) of the pixel (1) and the N-type semiconductor region (12) of the pixel (2); a pixel circuit that is arranged within the N-type well (15); and an inter-pixel isolation region (32) that is arranged between the N-type semiconductor region (13) of the pixel (1) and the N-type semiconductor region (13) of the pixel (2). The N-type semiconductor regions (13) and the P-type semiconductor region (14) form avalanche multiplication regions (AM).
