SELECTIVE FLUSHING OF INSTRUCTIONS IN AN INSTRUCTION PIPELINE IN A PROCESSOR BACK TO AN EXECUTION-RESOLVED TARGET ADDRESS, IN RESPONSE TO A PRECISE INTERRUPT

摘要

Selective flushing of instructions in an instruction pipeline in a processor back to an execution-determined target address in response to a precise interrupt is disclosed. A selective instruction pipeline flush controller determines if a precise interrupt has occurred for an executed instruction in the instruction pipeline. The selective instruction pipeline flush controller determines if an instruction at the correct resolved target address of the instruction that caused the precise interrupt is contained in the instruction pipeline. If so, the selective instruction pipeline flush controller can selectively flush instructions back to the instruction in the pipeline that contains the correct resolved target address to reduce the amount of new instruction fetching. In this manner, as an example, the performance penalty of precise interrupts can be lessened through less instruction refetching and reduced delay in instruction pipeline refilling when the instruction containing the correct target address is already contained in the pipeline.

主权项

1. A selective instruction pipeline flush controller for a processor, the selective instruction pipeline flush controller configured to:
receive a precise interrupt comprising a resolved target address from an instruction processing system as a result of executing an instruction; determine if an instruction at the resolved target address is present in an instruction pipeline in the instruction processing system; and responsive to determining that the instruction at the resolved target address is in the instruction pipeline, selectively flush at least one instruction stored in the instruction pipeline back to a location of the instruction at the resolved target address stored in the instruction pipeline.