ULTRA-LOW POWER COMPARATOR WITH SAMPLING CONTROL LOOP ADJUSTING FREQUENCY AND/OR SAMPLE APERTURE WINDOW

摘要

To minimize average quiescent current for a desire voltage error in a comparator (100), an example method includes receiving a first voltage (104) and a reference voltage (106), outputting a second voltage (108) when the first voltage (104) is lower than the reference voltage (106), wherein the outputting of the second voltage (108) increases the first voltage (104), counting a number of clock cycles while the first voltage (104) is higher than the reference voltage (106), comparing the number of clock cycles to a maximum number of clock cycles and a minimum number of clock cycles, decreasing a frequency of a clock associated with the number of clock cycles when the number of clock cycles is above the maximum number of clock cycles, and increasing the frequency of the clock when the number of clock cycles is below the minimum number of clock cycles.