RELIABILITY TESTING METHOD

摘要

Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device. A series of dielectric layers are provided between the conductive substrate or redistribution layer, the conductive layers, and the silicon device.

主权项

1. A chip reliability testing method, comprising:
mounting a test chip, comprising a plurality of test circuits, on a test board, wherein mounting the test chip includes connecting each test circuit of the plurality of test circuits to a different pair of input and output terminals on the test board; and subjecting the test chip to a reliability test, wherein subjecting the test chip to a reliability test includes applying a test voltage to a first bump of the test circuit; and measuring an output voltage on a second bump of the test circuit, the second bump being connected to the first bump through:
a first contact pad connected to the first bump;a second contact pad connected to the second bump,a first conductive via connected, through a conductive substrate or redistribution layer, to the first contact pad,a second conductive via connected, through the conductive substrate or redistribution layer, to the second contact pad, wherein the conductive substrate or redistribution layer is over a plurality of dielectric and conductive layers, arranged over a silicon device, and whereinthe first conductive via and the second conductive via are separated from the silicon device by at least one of the plurality of dielectric layers, andthe first conductive via is connected to the second conductive via through a conductive layer above the at least one of the plurality of dielectric layers.