发明名称 |
SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS |
摘要 |
A semiconductor device includes: a receiving circuit which receives communication frames each transmitted with a first period or a second period that are different from each other and including a synchronization code and data; a logic circuit which has a first operation state in which the received communication frames are each processed as data other than a digital video signal, and a second operation state in which the received communication frames are each processed as the digital video signal; a detecting circuit which detects the synchronization code from each of the received communication frames; a measuring circuit which measures a period of the detected synchronization code; and a determining circuit which determines the measured period. The logic circuit substantially makes a transition to the first operation state or the second operation state according to a result of the determining. |
申请公布号 |
US2017076662(A1) |
申请公布日期 |
2017.03.16 |
申请号 |
US201415123087 |
申请日期 |
2014.12.17 |
申请人 |
JOLED INC. |
发明人 |
ISHII Hiroaki |
分类号 |
G09G3/3225;G09G3/3275;G09G3/3266 |
主分类号 |
G09G3/3225 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor device which controls display of a display panel, the semiconductor device comprising:
a receiving circuit which receives a plurality of communication frames each transmitted with a first period or a second period and including a synchronization code and data, the first period and the second period being different from each other; a logic circuit which has a first operation state in which the plurality of communication frames received by the receiving circuit are each processed as data other than a digital video signal, and a second operation state in which the plurality of communication frames received by the receiving circuit are each processed as the digital video signal; a detecting circuit which detects the synchronization code from each of the plurality of communication frames received by the receiving circuit; a measuring circuit which measures a period of the synchronization code detected in each of the plurality of communication frames; and a determining circuit which determines whether the period measured is the first period or the second period, wherein the logic circuit substantially makes a transition to the first operation state or the second operation state according to a result of the determining performed by the determining circuit. |
地址 |
Tokyo JP |