| 发明名称 |
EMBEDDED MEMORY IN INTERCONNECT STACK ON SILICON DIE |
| 摘要 |
A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein. |
| 申请公布号 |
US2017077389(A1) |
申请公布日期 |
2017.03.16 |
| 申请号 |
US201415122911 |
申请日期 |
2014.06.16 |
| 申请人 |
INTEL CORPORATION |
发明人 |
NELSON Donald W.;WEBB M Clair;MORROW Patrick;JUN Kimin |
| 分类号 |
H01L43/02;H01L27/22;H01L43/12;H01L43/08;H01L43/10 |
主分类号 |
H01L43/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer comprising a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects comprises embedding memory devices therein; and coupling ones of the memory devices to each of respective ones of the plurality of first interconnects and the plurality of second interconnects and to ones of the plurality of circuit devices. |
| 地址 |
Santa Clara CA US |
